Jing Wang (王京)
I am a PhD student in Electrical and Computer Engineering (ECE) at the Hong Kong University of Science and Technology (HKUST). I am supervised by Prof. Zhiyao Xie. My research explores how AI can support RTL generation, circuit reasoning, and design automation. You can also call me Sebastian.
Research areas
RTL generation
AI for EDA
Circuit foundation models
01 / Education
2024–present
PhD in Electrical and Computer Engineering (ECE)
Hong Kong University of Science and Technology
2022–2024
Master of Science in Artificial Intelligence
The University of Hong Kong
2018–2022
Bachelor of Science in Electrical Information Engineering
Peking University
02 / Publications
First-author papers
CorrectRTL: Boost RTL Generation Quality Through Automated Self-Correction with Instruction Decomposition
IEEE/ACM International Conference on Computer Aided Design
A Survey of Circuit Foundation Model: Foundation AI Models for VLSI Circuit Design and EDA
ACM Transactions on Design Automation of Electronic Systems · † Co-first authors
RTL-BenchMT: Dynamic Maintenance of RTL Generation Benchmark Through Agent-Assisted Analysis and Revision
ACM/IEEE Design Automation Conference
HLSDebugger: Identification and Correction of Logic Bugs in HLS Code with LLM Solutions
IEEE/ACM International Conference on Computer Aided Design
SynCircuit: Automated Generation of New Synthetic RTL Circuits Can Enable Big Data in Circuits
ACM/IEEE Design Automation Conference · † Co-first authors